Resistive switching elements, such as electrolytic elements using conductive bridges, have been proposed as replacements for the configuration random access memory (“CRAM”) and pass gate transistor switches commonly found in integrated circuits (“ICs”) that have programmable elements. An example of such an IC is a field programmable gate array (“FPGAs”). Resistive switching elements are not necessarily limited to conductive bridge devices and the terms “resistive switches” and “programmable resistive switches” as used herein refer generally to a resistive element than can be configured to operate in one of at least two modes including a high impedance mode (where the resistive element essentially acts as a switch in an OFF state) and a low impedance mode (where the resistive element essentially acts as a switch in an ON state).
In past FPGA routing architectures, various levels of selection circuits (e.g., multiplexers or “muxes”) have been used to route signals between the main routing lines (e.g., horizontal and vertical channels of lines that span logic regions, e.g., logic array blocks or “LABs”) and the logic element inputs within each LAB. For example, in some architectures, a first level of mux into a LAB (sometimes referred to as a LAB input mux or “LIM”) can be programmed to select signals from a subset of routing lines and then a subset of the lines selected by the LIM can be selected by programming a second level mux, which is sometimes referred to as a logic element input mux or “LEIM”). A separate mux (sometimes referred to as a driver input mux or “DIM”) selects output from the logic element outputs and provides it to routing line drivers. In some implementations, the DIM may also select input from other routing lines in addition to selecting input from a local LABs outputs.
The programmable switches for selection circuits such as the LIMs, LEIMs, and DIMs described above have often been implemented with a CRAM element coupled to a pass gate transistor, the CRAM element holding a “1” or “0” that controls the transistor to be either on or off.
CRAM elements for programming selection circuits and for use in programming logic elements typically comprise a programmable array across a programming region of the FPGA. In a typical implementation, the array is programmed one column at a time. During a programming cycle, one column is selected (based on address data in an address register) and row programming data that has been loaded into data register elements is moved into the CRAM elements in the selected column. Within a programming region, an entire column of CRAM is programmed in a single clock cycle and such programming requires relatively little power. The column is selected using a single driver in conjunction with an address register.
Given the die cost of CRAM elements and associated pass gate transistors, existing routing structures typically only provide potential connections for a small subset of the routing resources in the vicinity of a LAB into that LAB's logic resources. For example, in some implementations, although substantially all of the routing lines in horizontal and vertical channels adjacent to a LAB are connected to a LIM input in that LAB, the LAB's LIM switch population only provides for about 5% of the possible LIM input to output connections.
Embodiments of the invention arise in this context.